1. Field of the Invention
The present invention relates to a computer graphic system, and in particular to a texture mapping system which can access texture data in parallel.
2. Description of the Background Art
In general, a computer graphic system is employed to display various graphical objects, such as points, lines, polygons and tree-dimensional objects, on a screen. In addition, in the computer graphic system, a texture mapping system (semiconductor chip) receives various texture data, and performs a texture mapping operation.
FIG. 1 is a block diagram illustrating a conventional texture mapping system. As shown therein, the texture mapping system includes: a memory controller 10 performing various control operations; a main memory 11 storing filtered texture images; a cache memory 12 storing a recently-used texture data; and an interpolator 13 forming a pixel from the texture data read from the cache memory 12.
The main memory 11 consists of a DRAM array, and the cache memory 12 has a sequential storage structure as shown in FIG. 3.
The operation of the conventional texture mapping system will now be described with reference to the accompanying drawings.
All filtered texture images applied to the graphic are stored in the main memory 11.
When a read address is inputted from a Rasterizer (not shown), the memory controller 10 accesses a specific row of the main memory 11, and outputs a write address to the cache memory 12 at the same time. As a result, data of the texture image filed in the main memory 11 as Mxc3x97N bits as shown in FIG. 2 are sequentially stored in the cache memory 12 as shown in FIG. 3. Here, one texture data is allotted to one write address. Accordingly, the above-described operation is repeatedly performed, and thus the texture images stored in the main memory 11 are stored in the cache memory 12 as the texture data.
In the texture mapping, the memory controller 10 outputs the read address to the cache memory 12, thereby accessing the texture data. One texture data is allotted to one read address. Accordingly, the interpolator 13 interpolates the texture data read from the cache memory 12, and forms and outputs the pixel data to a display unit.
However, in a three-dimensional graphic, the number of the texture data which the interpolator 13 must read from the cache memory 12 in regard to one pixel is varied according to filtering methods. For example, in a point sampling mode, the interpolator 13 reads one texture data from the cache memory 12, and forms one pixel data. In a bi-linear sampling mode, the interpolator 13 reads four adjacent texture data from the cache memory 12, and forms one pixel data.
Therefore, in the point sampling mode, the memory controller 10 accesses the cache memory 12 one time in order to process one pixel. On the other hand, in the bi-linear sampling mode, the memory controller 10 accesses the cache memory 12 four times in order to process one pixel. As a result, the access number to the cache memory 12 is more increased in the bi-linear sampling mode that the point sampling mode, thus deteriorating the three-dimensional graphic performance approximately by four times.
Accordingly, in the conventional texture mapping system, in case a few texture data are necessary in regard to one pixel (bi-linear or tri-linear), the cache memory must be accessed as many as the number of the texture data, which results in decreased performance of the three-dimensional graphic system.
It is therefore a primary object of the present invention to provide a texture mapping system which can improve three-dimensional graphic performance.
It is another object of the present invention to provide a texture mapping system which can read two texture data in parallel per access.
In order to achieve the above-described objects of the present invention, there is provided a texture mapping system including: a memory controller; a main memory storing filtered texture images; a cache memory receiving data of the texture image from the main memory, and separately storing texture data in odd-number columns and even-number columns; a texture address converter converting an address from the memory controller, and generating a read/write address of the cache memory; and an interpolator interpolating the texture data outputted from the cache memory, and forming a pixel data.